A power conductor is a large-capacity semiconductor which exhibits a voltage or a current larger than a voltage or a current used in a semiconductor for a personal computer or the like and has been popularly used in an electric power field, rail roads, automobiles, household electric appliances and the like,
Among modules which use such a power semiconductor, in a module-of a power transistor semiconductor of a general-purpose inverter having a capacitance of 0.1 kW to 5.5 kW which is used as a control device for various motors, power transformers or the like, a lead frame made of copper alloy has been conventionally used to decrease an electric resistance value of wiring and, at the same time, to obtain the excellent thermal characteristics.
FIG. 4 shows one example of the conventional structure of the semiconductor module which uses a semiconductor chip which constitutes one of power semiconductors and is referred to as an insulation gate type bipolar transistor (IGBT).
The semiconductor module is mainly constituted of a heat radiation plate 83 which is joined to a substrate 80, a semiconductor chip 90 which is joined to the heat radiation plate 83, and a lead frame 95 which has one end thereof joined to the semiconductor chip 90.
Electrodes are formed on both front and back surfaces of the semiconductor chip 90, wherein the collector electrode 91 is formed on the back surface of the semiconductor chip 90 and an emitter electrode 92 is formed on the front surface of the semiconductor chip 90. Further, the heat radiation plate 83 is joined to the collector electrode 91 on the back surface of the semiconductor chip 90 using a high-temperature solder layer 71. Still further, a lower surface of the heat radiation plate 83 is joined to a collector-side electrode 81 formed on the printed wiring board 80 using a low-temperature solder layer 72.
On the other hand, to an emitter electrode 92 formed on the surface of the semiconductor chip 90, one end of the lead frame 95 is joined using a high-temperature solder layer 73. Further, another end of the lead frame 95 is joined to a lead frame electrode 82 formed on the printed wiring board 80 using a low-temperature solder layer 74.
The manufacturing method of this power semiconductor module is as follows. First of all, in a non-oxidizing atmosphere using a carbon jig, the heat radiation plate 83, the semiconductor chip 90 and one end of the lead frame 95 are integrally formed by a joining step using the high-temperature solder layers 71, 73.
Next, in a reflow step which uses cream solder, the lower surface of the heat radiation plate 83 and another end of the lead frame 95 are respectively joined to the collector-side electrode 81 and the lead frame electrode 82 which are formed on the printed wiring board 80 by the low-temperature solder layers 72, 74 whereby a power semiconductor module having the structure shown in FIG. 4 is manufactured.
Here, as a conventional structural example of the semiconductor module which uses the semiconductor chip of insulation gate type bipolar transistor (IGBT) but differs from the semiconductor module shown in FIG. 4, the constitution shown in FIG. 5 is also known.
The semiconductor module shown in FIG. 5 mainly includes a circuit board 280 which is joined to a heat radiation plate 283 and is formed of a DBC substrate, a semiconductor die 290 which is joined to the circuit board 280 and is formed of a semiconductor chip, and a bonding wire 295 which has one end thereof joined to the semiconductor die 290.
Electrodes are formed on both front and back surfaces of the semiconductor die 290, wherein a back-surface die electrode 291 which constitutes a collector electrode is formed on the back surface of the semiconductor die 290 and a front-surface die electrode 292 which constitutes an emitter electrode is formed on a surface of the semiconductor die 290. Further, the heat radiation plate 283 is made of a metal material such as Cu or the like, while the circuit board 280 which is formed of the DBC substrate is constituted by forming electrodes 280 B, 280 C and 280 D formed of a conductive layer made of Cu or the like on both surfaces of a ceramic substrate 280A.
To the back surface die electrode 291 of the semiconductor die 290, a first circuit electrode 280 B which constitutes a collector conductive layer on an upper surface of the circuit board 280 is joined by means of a joining portion 271, and a third circuit electrode 280 D which constitutes a heat-radiation-plate conductive layer formed on a lower surface of the circuit board 280 is joined to the heat radiation plate 283 by means of a joining portion 272.
On the other hand, a front-surface die electrode 292 of the semiconductor die 290 and a second circuit board 280 C which constitutes a lead-frame conductive layer formed on an upper surface of the circuit board 280 are joined by a bonding wire 295.
Then, the above-mentioned joining portions 271, 272 constitute joining portions formed by solder joining.
Further, with respect to a technique relevant to the formation of the above-mentioned solder layer, a method which forms solder bumps made of alloy by a vapor deposition method has been known. For example, as a method for forming lead-free solder bumps due to the formation of a multilayered film, JP-A-2002-43348 discloses a technique in which an Sn film and an M film whose film thicknesses are set to obtain the composition of Sn1−XMX (M: containing at least one of Au, In and x being set to satisfy the relationship of 0<x<0.5) are alternately vapor-deposited to form a multilayered film and, thereafter, a mask is removed to form a solder bump precursor which is formed of the above-mentioned multilayered film, subsequently, annealing is applied to the solder bump precursor to make the composition of the solder bump precursor uniform and, further, the solder bump precursor is subject to the reflow at an eutectic temperature of the precursor thus forming the solder bumps.
Further, JP-A-5-9713 discloses an alloy vapor deposition method in which base alloy whose composition and quantity are adjusted to obtain an alloy film of desired composition and desired thickness is preliminarily prepared in a crucible for vapor deposition, and the base alloy is completely evaporated to form a targeted alloy film on a substrate and, at the same time, the base alloy composition for vapor-depositing alloy having the targeted composition is preliminarily obtained thus obtaining a vapor deposited film of alloy having the arbitrary composition.
In the above-mentioned manufacturing method of a power semiconductor module using the solder which constitutes the prior art, as explained in conjunction with the example shown in FIG. 4, for example, the manufacturing method includes steps which perform heating twice, that is, the joining step which uses the high-temperature solder and the step which performs solder joining using the cream solder having a melting point lower than a melting poring of the high-temperature solder. Here, particularly in the joining step which uses the high-temperature solder, a high temperature of approximately 300° C. is required and hence, there arises a drawback that the semiconductor die is liable to be easily damaged by heat generated at the time of joining. Further, there also exists a drawback that the steps become complicated since two kinds of solders, that is, the high-temperature solder and the low-temperature solder are used.
Further, the power semiconductor module allows a large current to pass therethrough and hence, the power semiconductor module generates heat remarkably whereby a thermal stress arises due to the difference in thermal expansion rate among respective constitutional materials. For example, in the conventional solder joining used in the examples shown in FIG. 4 and FIG. 5, there has been a drawback that a joining interface is broken by this thermal stress.
Still further, the reliability of the joining portion such as the strength, fatigue lifetime depends on the property of a material which is interposed between parts to be joined and a solder material has a drawback with respect to the high-temperature property and the thermal fatigue lifetime. Particularly, with respect to a die such as the power semiconductor module to which a large current is applied, there exists a possibility of the lowering of the insulating property of the power semiconductor module attributed to an organic material and hence, it is impossible to use a flux which serves to remove surface oxide of a joining material thus joining the parts. Accordingly, in the conventional solder joining, there has been a drawback that a defect of several 100 μm level may occur in the joining portion attributed to contamination or oxide during a joining step.
Further, in the method for forming the lead-free solder bumps disclosed in JP-A-2002-43348, the joining at a low temperature for a short time is insufficient. For example, the joining at a low temperature of 200° C. or less and for a short time is difficult.
Further, in the alloy vapor deposition method of the JP-A-5-9713, it is necessary to obtain the relationship between the composition of the base alloy in the crucible and the alloy composition in the vapor-deposited film and, it is necessary to determine the composition of the base alloy based on a correction curve thus giving rise to a drawback that the preparation steps up to the vapor deposition becomes cumbersome.
The present invention has been made in view of these drawbacks and it is an object of the present invention to provide a manufacturing method of a semiconductor module which enables the joining of an electrode of a semiconductor die, an electrode on a circuit board, a connecting member such as a lead frame and, further, a heat radiating member at a low temperature within a short time, and can obtain a highly reliable joining portion by performing the joining without using a solder joining medium.